Concurrent Error Detection and Correction for Orthogonal Latin Squares Encoders and Syndrome Computation

In advanced electronic circuits the reliability has been a major concern. There are number of mitigation techniques proposed to make sure that the errors do not affect the circuit functionality. Among them, to protect the memories and registers in electronic circuits Error Correction Codes (ECC) are commonly used. Whenever any ECC technique is used, the encoder and decoder circuit may also suffer errors. In this brief, concurrent error detection and correction technique for OLS encoders and syndrome computation is proposed and evaluated. The proposed method efficiently implements a parity prediction scheme that detects all errors that affect a single circuit node using the properties of OLS codes. The results constitute simulation of Verilog codes of different modules of the codes in Xilinx 13.2. The results demonstrate that the CED for OLS encoders & Syndrome Computation are very efficient for the detection and correction of burst errors.